Microcontrollers BCS402
Course Code: BCS402
Credits: 04
CIE Marks: 50
SEE Marks: 50
Total Marks: 100
Exam Hours: 03
Total Hours of Pedagogy: 40T + 12L
Teaching Hours/Weeks: [L:T:P:S] 3:0:2:0
ARM Embedded Systems: The RISC design philosophy, The ARM Design Philosophy, Embedded
System Hardware, Embedded System Software.
ARM Processor Fundamentals: Registers, Current Program Status Register, Pipeline, Exceptions,
Interrupts, and the Vector Table, Core Extensions.
MODULE-2
Introduction to the ARM Instruction Set: Data Processing Instructions, Branch Instructions, Software Interrupt Instructions, Program Status Register Instructions, Coprocessor Instructions, Loading Constants.
MODULE-3
C Compilers and Optimization: Basic C Data Types, C Looping Structures, Register Allocation, Function Calls, Pointer Aliasing, Portability Issues.
MODULE-4
Exception and Interrupt Handling: Exception handling, ARM processor exceptions and modes, vector
table, exception priorities, link register offsets, interrupts, assigning interrupts, interrupt latency, IRQ and FIQ exceptions, basic interrupt stack design and implementation.
Firmware: Firmware and bootloader, ARM firmware suite, Red Hat redboot, Example: sandstone, sandstone
directory layout, sandstone code structure.
MODULE-5
Caches: The Memory Hierarchy and Cache Memory, Caches and Memory Management Units: CACHE
Architecture: Basic Architecture of a Cache Memory, Basic Operation of a Cache Controller, The
Relationship between Cache and Main Memory, Set Associativity, Write Buffers, Measuring Cache
Efficiency.
Cache Policy: Write Policy—Writeback or Writethrough, Cache Line Replacement Policies,
Allocation Policy on a Cache Miss. Coprocessor 15 and caches.
This time the resources have been uploaded earlier which is useful
This is very useful for our studies thanks to you..
Pls upload other module notes of mc
Please provide short notes
short notes is difficult to provide…
module 03 and 05 upload
Your writing style makes complex topics seem simple. Thanks!
please update the notes pdf as 1st module .